教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
學年85
學期2
發表日期1997/06/09
作品名稱A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
作品名稱(其他語言)
著者鄭國興; Cheng, Kuo-hsing; Yee, Liow-yu; Chen, Jian-hung
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
會議地點Hong Kong
摘要In this paper, a new circuit interconnection scheme of the low-power current-sensing complementary pass-transistor logic (LCSCPTL) is proposed and analyzed. The proposed new circuit scheme using full-swing and non-full-swing output signals to control the NMOS pass transistor logic tree network. Due to the non-full-swing outputs and the current-sensing scheme, the new logic circuit scheme can improve the power dissipation and operation speed. The non-full-swing LCSCPTL is applied to the design of the parallel multiplier. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V 8×8-bit parallel multiplier can be fabricated without changing the conventional 5 V CMOS process. The operation speed of the parallel multiplier is 32 ns for 1.2 V supply voltage.
關鍵字
語言英文
收錄於
會議性質
校內研討會地點
研討會時間19970609~19970612
通訊作者
國別香港
公開徵稿
出版型式
出處Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol.3, pp.1948-1951
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