| An efficient mechanism for debugging RTL description | |
|---|---|
| 學年 | 91 |
| 學期 | 2 |
| 發表日期 | 2003-06-30 |
| 作品名稱 | An efficient mechanism for debugging RTL description |
| 作品名稱（其他語言） | |
| 著者 | Ran, Jiann-chyi; Chang, Yi-yuan; Lin, Chia-hung |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on |
| 會議地點 | Calgary, Alta., Canada |
| 摘要 | In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | |
| 校內研討會地點 | |
| 研討會時間 | 20030630~20030702 |
| 通訊作者 | |
| 國別 | CAN |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on, pp.370-373 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/39041 ) |
| SDGS | 產業創新與基礎設施 |
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