The Improvement of Conditional Sum Adder for Low Power Applications
學年 87
學期 1
發表日期 1998-09-13
作品名稱 The Improvement of Conditional Sum Adder for Low Power Applications
作品名稱(其他語言)
著者 鄭國興; Cheng, Kuo-hsing; Chiang, Shu-min; Cheng, Shun-wen
作品所屬單位 淡江大學電機工程學系
出版者 Piscataway: Institute of Electrical and Electronics Engineers
會議名稱 ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
會議地點 Rochester, NY, USA
摘要 The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 19980913~19980916
通訊作者
國別 USA
公開徵稿
出版型式
出處 ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International, pp.131-134
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