教師資料查詢 | 類別: 期刊論文 | 教師: 吳柏翰 WU PO-HAN (瀏覽個人網頁)

標題:Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
學年99
學期1
出版(發表)日期2010/09/01
作品名稱Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
作品名稱(其他語言)
著者Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun
單位淡江大學電機工程學系
出版者臺北縣淡江大學
著錄名稱、卷期、頁數淡江理工學刊=Tamkang Journal of Science and Engineering 13(3)頁305-314
摘要In this paper, we propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. The control signal combination causes the computing time increasing exponentially, and the algorithm we proposed introduces a heuristic control signal selecting method to solve this serious problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. The results show that it could significantly reduces both the test application time and the computation time.
關鍵字
語言英文
ISSN1560-6686
期刊性質國內
收錄於EI;
產學合作
通訊作者Rau, Jiann-Chyi
審稿制度
國別中華民國
公開徵稿
出版型式,紙本
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