教師資料查詢 | 類別: 期刊論文 | 教師: 吳柏翰WU PO-HAN (瀏覽個人網頁)

標題:A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
學年96
學期2
出版(發表)日期2008/06/01
作品名稱A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
作品名稱(其他語言)
著者Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu
單位淡江大學電機工程學系
出版者臺北縣:淡江大學
著錄名稱、卷期、頁數淡江理工學刊=Tamkang journal of science and engineering 11(2),頁175-184
摘要During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns can't detect fault (called useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In fact, a random test set includes many useless patterns. Therefore we present a technology, including both reseeding and bit modifying (a.k.a. pattern mapping) to remove useless patterns or change them to useful patterns. When patterns changed, we pick out number of different fewer bits, leading to very short test length. Then we use an additional bit counter to improve test length and achieve high fault coverage. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with less test time.
關鍵字
語言英文
ISSN1560-6686
期刊性質國際
收錄於EI;
產學合作
通訊作者Rau, Jiann-chyi
審稿制度
國別中華民國
公開徵稿
出版型式紙本
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