教師資料查詢 | 類別: 期刊論文 | 教師: 吳柏翰 WU PO-HAN (瀏覽個人網頁)

標題:Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
學年99
學期1
出版(發表)日期2011/01/01
作品名稱Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
作品名稱(其他語言)
著者Rau, Jiann-Chyi; Wu, Po-Han
單位淡江大學電機工程學系
出版者Stevenage: The Institution of Engineering and Technology
著錄名稱、卷期、頁數IET Computers &; Digital Techniques 5(1), pp.25-35
摘要As the test data continues to grow quickly, test cost also increased. For the sake of decreasing the test cost, this study presents a new compression for large circuit, which is based on multiple scan-chains and unknown structure. The proposed method is targeted at intellectual property cores and system-on-a-chip. The authors consider the shift-in power and compression ratio in low-cost automatic test equipment (ATE) environment. A new compression architecture with fixed length for running ones is proposed. For the proposed method, the ATE has no repeated function and synchronisation signal. In the results, when the complexity of very large-scale integrated circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest and TetraMAX on ISCAS'89 benchmarks. The average of peak/weight transition count shift-in turns to 3x/6.6x for MinTest and 2.3x/5.6x for TetraMAX, after comparing selective scan slice and the proposed method. The average of hardware overhead is 6% for MinTest and 6.5% for TetraMAX.
關鍵字
語言英文
ISSN1751-8601
期刊性質國外
收錄於SCI;EI
產學合作
通訊作者Rau, Jiann-Chyi
審稿制度
國別英國
公開徵稿
出版型式紙本
相關連結
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