教師資料查詢 | 類別: 期刊論文 | 教師: 余 繁 YU FUN (瀏覽個人網頁)

標題:Dynamic Bias Circuits for Efficiency Improvement of RF Power Amplifier
學年93
學期1
出版(發表)日期2004/09/01
作品名稱Dynamic Bias Circuits for Efficiency Improvement of RF Power Amplifier
作品名稱(其他語言)
著者余繁; Ye, Fun; Chiang, Jen-shiun; Chen, Chun-wen; Sung, Yu-chen
單位淡江大學電機工程學系
出版者淡江大學
著錄名稱、卷期、頁數淡江理工學刊=Tamkang journal of science and engineering 7(3), pp.183-188
摘要This work presents a dynamic gate bias circuit for bias control to maximize power added efficiency based on the class-A two-stage power amplifier. The proposed circuits are composed of two NMOS transistors, a capacitor for coupling RF input signal, and four resistors for bias. The circuit is implemented by means of the bias control at the two-stage power amplifier to improve the overall power added efficiency and delivers 22dBm output power at 2.4 GHz. The circuit can improve power efficiency and linearity for small RF signals. The simulation indicates that the efficiency is improved more than 100%, and at 0 dBm the input signal has 515dB of IMD3 improvement compared with that without dynamic bias circuit. The output power of 22dBm at the output stage can be applied to the transceivers of IEEE 802.11b and Bluetooth applications.
關鍵字CMOS;Dynamic Bias Circuits;Linearity;Power Added Efficiency;Power Amplifie;RF
語言英文
ISSN1560-6686
期刊性質國內
收錄於
產學合作
通訊作者
審稿制度
國別中華民國
公開徵稿
出版型式,電子版
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