教師資料查詢 | 類別: 期刊論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A Novel SOPC-Based CMOS Image Sensor Testing System
學年100
學期2
出版(發表)日期2012/05/01
作品名稱A Novel SOPC-Based CMOS Image Sensor Testing System
作品名稱(其他語言)
著者Li, Shin-an; Chiang, Jen-shiun; Chen, Kuang-yuan; Liu, Ta-kang; Wong, Ching-chang
單位淡江大學電機工程學系
出版者Valencia: American Scientific Publishers
著錄名稱、卷期、頁數Sensor Letters 10(5-6), pp.1068-1074
摘要Since CMOS Image Sensor (CIS) has the characteristics of low cost and low power consumption as well as ease of integration with digital IC, the module size can thus be greatly reduced. Therefore, as the process evolutions, CMOS pixel capacity gets continuously enlarged, and it is thus wieldy used in all kinds of consumer products that need to record or detect the images. However, as the image quantity gets continuously enhanced, the test process of CIS gets more and more complicated, the needed test platform price and test time gets increased, which usually leads to serious burden on the test cost. The test procedure of CIS actually can be divided into traditional DC parameter test, functional test and the specific image test for CIS. However, the test platform associated the above two test functions hast is specific use, and the enhancement in the pixel capacity further leads to difficulty in reducing the test cost. This paper proposes a System On a Programmable Chip (SOPC) based CMOS image test platform to be associated with traditional function test platform to form a CIS test architecture. It not only can break the specific use of test platform, but also can reduce the test cost effectively. Moreover, due to the great reduction of image transmission distance, the image test quality can be greatly reduced.
關鍵字EMBEDDED PROCESSOR; FPGA; HW/SW CO-DESIGN; IMAGE ACCELERATOR; IMAGE PROCESS; SOPC
語言英文
ISSN1546-198X
期刊性質國外
收錄於SCI;
產學合作國外;
通訊作者
審稿制度
國別美國
公開徵稿
出版型式紙本,
相關連結
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