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標題:Low-power way-predicting cache using valid-bit pre-decision for parallel architectures
學年93
學期2
發表日期2005/03/28
作品名稱Low-power way-predicting cache using valid-bit pre-decision for parallel architectures
作品名稱(其他語言)
著者Chen, Hsin-Chuan; Chiang, Jen-Shiun
作品所屬單位淡江大學電機工程學系
出版者Los Alamitos, CaliforniaInstitute of Electrical and Electronics Engineers (IEEE)
會議名稱Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on
會議地點臺北縣, 臺灣
摘要Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By validbit pre-decision, it significantly helps in improving the average energy saving of the conventional waypredicting cache without valid-bit pre-decision, especially for with large associativity and small subblock size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點淡水校園
研討會時間20050328~20050330
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on, vol.2, pp.203-206
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