教師資料查詢 | 類別: 會議論文 | 教師: 林政曜 LIN, JHENG-YAO (瀏覽個人網頁)

標題:A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC
學年94
學期1
發表日期2005/08/03
作品名稱A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC
作品名稱(其他語言)
著者Lee, Yang-han; Jan, Yih-guagn; Shen, Jei-jung; Tzeng, Shian-wei; Chuang, Ming-hsueh; Lin, Jheng-yao
作品所屬單位淡江大學電機工程學系
出版者MTDT
會議名稱2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005)
會議地點Taipei, Taiwan
摘要This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20050803~20050805
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), pp.78-82
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