| A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC | |
|---|---|
| 學年 | 94 |
| 學期 | 1 |
| 發表日期 | 2005-08-03 |
| 作品名稱 | A DFT Architecture for a Dynamic Fault Model of The Embedded Mask ROM of SOC |
| 作品名稱（其他語言） | |
| 著者 | Lee, Yang-han; Jan, Yih-guagn; Shen, Jei-jung; Tzeng, Shian-wei; Chuang, Ming-hsueh; Lin, Jheng-yao |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | MTDT |
| 會議名稱 | 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005) |
| 會議地點 | Taipei, Taiwan |
| 摘要 | This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20050803~20050805 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), pp.78-82 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70228 ) |
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