教師資料查詢 | 類別: 會議論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:A New Low Power, High Speed Double-Edge Triggered Flip-Flop
學年96
學期2
發表日期2008/07/22
作品名稱A New Low Power, High Speed Double-Edge Triggered Flip-Flop
作品名稱(其他語言)
著者Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung
作品所屬單位淡江大學電機工程學系
出版者
會議名稱2008亞太華人高速電路設計研討會(HSCD 2008)
會議地點臺北縣, 臺灣
摘要In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74% in compared with others.;In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74 % in compared with others.
關鍵字double-edge triggered;low power;high speed Best Regards;Double-edge triggered;Low power;High speed Best Regard
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20080722~20080723
通訊作者
國別中華民國
公開徵稿
出版型式紙本
出處2008亞太華人高速電路設計研討會(HSCD 2008)論文集5頁
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