A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
學年 92
學期 1
發表日期 2003-08-12
作品名稱 A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
作品名稱（其他語言）
著者 Cheng, Kuo-Hsing; Li, Po-Yu; Chen, Tsung-Shen
作品所屬單位 淡江大學電機工程學系
出版者
會議名稱 第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium
會議地點 花蓮縣, 臺灣
摘要 In this paper, a 14-bit, low DNL error, 200M sample/s, current-steering digital to analog converter without trimming is proposed and analyzed. A novel feedback gain stage current mirror is proposed for improving the DAC's differential non-linearity (DNL) and integral nonlinearity(INL) characteristic. The proposed current steering DAC is designed and an experimental chip was implemented based on the TSMC 0.25um 1P5M CMOS process with a 2.5V supply voltage The post-layout simulation results show that both the DNL and INL oft his DAC are good. The DNL and INL are better than �0.06 least significant bit (LSB) and �0.06 0LSB, respectively.
關鍵字 數位類比轉換器;修剪;差動非線性誤差;累增非線性誤差;最小位元;Digital analog converter (DAC);Trimming;Differential non-linearity(DNL);Integral non-linearity (INL);Least significant bit (LSB)
語言 en
收錄於
會議性質 國內
校內研討會地點
研討會時間 20030812~20030815
通訊作者
國別 TWN
公開徵稿 Y
出版型式 紙本
出處 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁205-208
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