| The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer | |
|---|---|
| 學年 | 86 |
| 學期 | 1 |
| 發表日期 | 1997-08-21 |
| 作品名稱 | The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer |
| 作品名稱（其他語言） | |
| 著者 | Cheng, Kuo-Hsing; Yang, Wei-Bin; Huang, Hong-Yi |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 第八屆超大型積體電路設計暨計算機輔助設計技術研討會=The 8th VLSI Design/CAD Symposium |
| 會議地點 | 南投縣, 臺灣 |
| 摘要 | A new low-power hihg-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer is proposed. By using the feedback-controlled split- path method, the short-circuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is saving of over 20 % in comparison to conventional CMOS tapper buffer at 100MHz operation frequency. |
| 關鍵字 | 電荷轉移;回授控制;分徑;緩衝器;互補式金氧半導體;Charge Transfer;Feedback Control;Split Path;Buffer;Cmos |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 19970821~19970823 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium，頁353-356 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96025 ) |
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