教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
學年86
學期1
發表日期1997/08/21
作品名稱A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
作品名稱(其他語言)
著者Cheng, Kuo-Hsing; Chen, Jian-Hung
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第八屆超大型積體電路設計暨計算機輔助設計技術研討會=The 8th VLSI Design/CAD Symposium
會議地點南投縣, 臺灣
摘要This paper describes a new low-voltage low-power TSPC complementary pass-transistor logic circuit for 1.2V applications. The proposed logic circuits are implemented with only NMOS differential pass- transistor logic network and controlled by true-single-phase clock signal to form the pipelined structures. Due to the limited voltage swing and current-sensing scheme, the proposed TSPC logic circuits have certain advantages in both operation speed and power dissipation. Moreover, it can be designed and fabricated without changing the conventional 5V, 0.6μm CMOS process. Based upon the HSPICE simulation results the differential-input TSPC structure reach a 185MHz operation frequency in a adder circuit for 1.2V supply voltage.
關鍵字互補式被動電晶體邏輯;真實單相時序;低功率;緩衝器;電路模擬;Complementary Pass-Transistor Logic;True-Single-Phase Clock;Low Power;Buffer;Circuit Simulation
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19970821~19970823
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium頁357-360
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