| Low-Voltage GHz Dynamic Logic Circuit Design | |
|---|---|
| 學年 | 91 |
| 學期 | 1 |
| 發表日期 | 2002-08-12 |
| 作品名稱 | Low-Voltage GHz Dynamic Logic Circuit Design |
| 作品名稱（其他語言） | |
| 著者 | Cheng, Kuo-Hsing; Lee, Wen-Shiuan |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 2002年超大型積體電路設計暨計算機輔助設計技術研討會=2002 VLSI Design/CAD Symposium |
| 會議地點 | 臺東市, 臺灣 |
| 摘要 | In this paper, an All-N-Block true single phase clocking logic(ANTSPC) for high operation speed and high packing density application is proposed. The ANTSPC has several advantages. Because the internal node is non-full voltage swing, it can save the dynamic power dissipation. Owing to the logic block is designed by the NMOS transistors instead of the PMOS transistors, therefore, the output loading of the Φ-Section can be reduced and the packing density of the chip is higher. Thus, the operation speed of whole pipelined system is faster than which is designed by the conventional TSPC. Finally, a 8-bit CLA adder using 0.35.mu.m 1P4M CMOS technology with 2.5V power supply could be operated on 1.25GHz clock frequency and the power/Max. frequency is 10.88 uW/MHz. |
| 關鍵字 | 邏輯電路設計;低電壓;功率消耗;Logic Circuit Design;Low Voltage;Power Dissipation |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 20020812~20020815 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁113-116 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95894 ) |
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