教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A Jitter-Free Phase-Interpolation Direct Digital Synthesizer Using Two-Phase Integration
學年92
學期1
發表日期2003/08/12
作品名稱A Jitter-Free Phase-Interpolation Direct Digital Synthesizer Using Two-Phase Integration
作品名稱(其他語言)
著者Chen, Hsin-Chuan; Chiang, Jen-Shiun; Chen, Hsing-Ying
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium
會議地點花蓮縣, 臺灣
摘要There exists a phase jitter problem in using the conventional direct digital frequency synthesizer (DDS)as a pulse or clock generator, and most of the existed solving methods employ the phase interpolation to generate a pulse or clock with correct time intervals. In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the adder within the phase accumulator to provide an initial voltage on an integration capacitor in the first phase, and then performs integration operation on the integration capacitor in the second phase. Therefore, this DDS can correct the phase error at each overflow of the phase accumulator. Furthermore, no ROM tables and D/A converters are required, the proposed DDS using a two-phase integration not only provides a jitter-free clock output to reduce its spurious level, but also has a low hardware complexity.
關鍵字無震盪;相位插入;直接數位合成器;二相位積分;數位類比轉換器;鎖相迴路;Jitter-free;Phase-interpolation;Direct digital synthesizer (DDS);Two-phase integration;Digital analog converter (DAC);Phase lockedloop (PLL)
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20030812~20030815
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium頁565-568
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