教師資料查詢 | 類別: 會議論文 | 教師: 江正雄CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A High Speed Radix-4 Carry Free Division Architecture
學年89
學期1
發表日期2000/08/16
作品名稱A High Speed Radix-4 Carry Free Division Architecture
作品名稱(其他語言)
著者Chiang, Jen-Shiun; Tsai, Min-Shiou; Chiu, Yi-Fang
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第十一屆超大型積體電路設計暨計算機輔助設計技術研討會=The 11th VLSI Design/CAD Symposium
會議地點屏東縣, 臺灣
摘要A novel floating-point division architecture with IEEE 754-1985 standard is proposed in this paper. This architecture is based on New Svoboda-Tung division algorithm and radix-4 MROR signed digit number system.The binary number to radix-4 MROR signed number conversion and prescaling of this divider are implemented together by a very simple scheme and they take very few cycle times. A new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. Based on this scheme, a 32-b/32-b divider is designed in Verilog HDL; the simulation result shows that this architecture is feasible to a real divider.
關鍵字浮點分割;Svoboda-Tung分割;標注數位碼系統;Floating-Point Division;Svoboda-Tung Division;Signed Digit Number System
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20000816~20000819
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第十一屆超大型積體電路設計暨計算機輔助設計技術研討會技術論文集=Proceedings of the 11th VLSI Design/CAD Symposium,頁175-178
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