| A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme | |
|---|---|
| 學年 | 95 |
| 學期 | 1 |
| 發表日期 | 2006-08-08 |
| 作品名稱 | A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme |
| 作品名稱（其他語言） | |
| 著者 | Jan, Yih G.; Chiang, Jen-Shiun; Tsai, Ming-Chi; Chen, Hsin-Liang; Chang, Yao-Tsung |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 第17屆超大型積體電路設計暨計算機輔助設計技術研討會=The 17th VLSI Design/CAD Symposium |
| 會議地點 | 新竹市, 臺灣 |
| 摘要 | In this paper, a low power wide bandwidth second-order continuous-time (CT) delta-sigma (.DELTA..SIGMA.) modulator with single amplifier scheme is presented. For low power consideration, we design this continuous-time modulator by the architecture of single-loop with 3-bit quantize and use only one amplifier. This continuous-time delta-sigma modulator achieves a 2 MHz signal bandwidth at 128 MHz sampling frequency operation with 68dB of dynamic range and 67.3dB of peak signal-to-noisedistortion ratio (PSNDR). The circuit is implemented by the standard 0.18-.mu.m 1P6M CMOS technology. The core area is 0.23mm/sup 2/ (0.36mm*0.64mm) and the power consumption is only 2.3-mW with 1.8-V power supply. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 20060808~20060811 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 第17屆超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of the 17th VLSI Design/CAD Symposium，4頁 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96006 ) |
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