教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme
學年95
學期1
發表日期2006/08/08
作品名稱A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme
作品名稱(其他語言)
著者Jan, Yih G.; Chiang, Jen-Shiun; Tsai, Ming-Chi; Chen, Hsin-Liang; Chang, Yao-Tsung
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第17屆超大型積體電路設計暨計算機輔助設計技術研討會=The 17th VLSI Design/CAD Symposium
會議地點新竹市, 臺灣
摘要In this paper, a low power wide bandwidth second-order continuous-time (CT) delta-sigma (.DELTA..SIGMA.) modulator with single amplifier scheme is presented. For low power consideration, we design this continuous-time modulator by the architecture of single-loop with 3-bit quantize and use only one amplifier. This continuous-time delta-sigma modulator achieves a 2 MHz signal bandwidth at 128 MHz sampling frequency operation with 68dB of dynamic range and 67.3dB of peak signal-to-noisedistortion ratio (PSNDR). The circuit is implemented by the standard 0.18-.mu.m 1P6M CMOS technology. The core area is 0.23mm/sup 2/ (0.36mm*0.64mm) and the power consumption is only 2.3-mW with 1.8-V power supply.
關鍵字
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20060808~20060811
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第17屆超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of the 17th VLSI Design/CAD Symposium4頁
相關連結
Google+ 推薦功能,讓全世界都能看到您的推薦!