| A Novel BIST Response Analyzer Based on TLS | |
|---|---|
| 學年 | 91 |
| 學期 | 1 |
| 發表日期 | 2002-08-12 |
| 作品名稱 | A Novel BIST Response Analyzer Based on TLS |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-Chyi; Jone, Wen-Ben |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 2002年超大型積體電路設計暨計算機輔助設計技術研討會=2002 VLSI Design/CAD Symposium |
| 會議地點 | 臺東市, 臺灣 |
| 摘要 | Built-In Self-Testing (BIST) of very large scale integrated circuits(VLSI) mainly consists of two components --- test pattern generator(TPG) and output response analyze (ORA). Hence, under BIST, each of the inserted bypass storage cell (bscs) needs two flip-flops. This paper presents a novel architecture for ORA. The advantages of such architecture are that most bscs need one instead of two flip- flops, leading to the less hardware overhead shown in the experimental results. |
| 關鍵字 | 內建自測試;測試圖樣產生器;輸出響應分析;超大型積體電路;Built-In Self-Testing;Test Pattern Generator;Output Response Analysis;Vlsi |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 20020812~20020815 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁396-399 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95895 ) |
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