教師資料查詢 | 類別: 會議論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:A Core-Based Test Methodology for Fast Multipliers
學年92
學期1
發表日期2003/08/12
作品名稱A Core-Based Test Methodology for Fast Multipliers
作品名稱(其他語言)
著者Rau, Jiann-Chyi; Lin, Chia-Hung; Lin, Ching-Hsiu
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium
會議地點花蓮縣, 臺灣
摘要To test core-based SoCs, an important step is to get the efficient test vectors for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test vectors at higher level than at logic level. For core vendors, they design their IP cores not only add design for testability (DFT) strategyf or its cores, but also provide the most effective test vectors for core users. Based on this issue, in this paper, we propose a method to generate pseudo-exhaustive test patterns at functional level. The proposed method can be used to generate test patterns for IP cores, especially, for soft IPs.
關鍵字快速多工器;測試策略;核心基礎;矽智產;系統單晶片;數位信號處理器;Fast multiplexer;Test strategy;Core-based;Intellectuall property(IP);System-on-a-chip (SOC);Digital signal processor (DSP)
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20030812~20030815
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium頁437-440
相關連結
Google+ 推薦功能,讓全世界都能看到您的推薦!