教師資料查詢 | 類別: 會議論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
學年92
學期1
發表日期2003/08/12
作品名稱Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
作品名稱(其他語言)
著者Rau, Jiann-Chyi; Kuo, Kuo-Chun; Yang, Ta-Wei
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium
會議地點花蓮縣, 臺灣
摘要As the test pattern requirement of a pseudo-exhaustive testing is fewer than the traditional exhaustive testing, many approaches and architectures are proposed to implement the pseudo-exhaustive testing. Although these methods and architectures employ LFSR to generate the exhaustive pseudo random test patterns could successfully cut down the test time, the same problem of invalid test patterns should still be considered. To avoid these invalidt est patterns, it requires new strategy to solve this problem. Since different seeds of the LFSR dominate different simulation results, seed selection is not arbitrary any more. A suggestive threshold stop point for new strategy, which tries to solve "invalid test patterns" problem, is defined in this paper. Based on the concept of careful seed selection, an enhanced tree-structured scan chain is proposed to shorten total test cycle time again.
關鍵字準徹底測試;超大規模積體電路;樹狀結構掃描鏈;線性回饋移位暫存器;待測電路;Pseudo-exhaustively testing;Very large scale integrated circuit(VLSI);Tree-structured scan chain;Linear feedback shift register(LFSR);Circuit under test (CUT)
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間20030812~20030815
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium頁305-308
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