A Datapath-Based Debugging Mechanism for RTL Description
學年 92
學期 1
發表日期 2003-08-12
作品名稱 A Datapath-Based Debugging Mechanism for RTL Description
著者 Rau, Jiann-Chyi; Chang, Yi-Yuan; Huang, Wang-Tiao
作品所屬單位 淡江大學電機工程學系
會議名稱 第十四屆超大型積體電路暨計算機輔助設計技術研討會=The 14th VLSI Design/CAD Symposium
會議地點 花蓮縣, 臺灣
摘要 In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
關鍵字 資料路徑;暫存器轉移層次;雜道層次;硬體描述語言;錯誤空間;Data-path;Register-transfer level (RTL);Gate level;Hardwaredescription language (HDL);Error space
語言 en
會議性質 國內
研討會時間 20030812~20030815
國別 TWN
公開徵稿 Y
出版型式 紙本
出處 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁153-156

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96037 )