| 標題：Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform |
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| 學年 | 101 |
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| 學期 | 2 |
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| 出版（發表）日期 | 2013/04/01 |
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| 作品名稱 | Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform |
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| 作品名稱（其他語言） | |
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| 著者 | Hsia, Chih-Hsien; Chiang, Jen-Shiun; Guo, Jing-Ming |
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| 單位 | 淡江大學電機工程學系 |
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| 出版者 | Piscataway:Institute of Electrical and Electronics Engineers |
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| 著錄名稱、卷期、頁數 | IEEE Transactions on Circuits and Systems for Video Technology 23(4), pp.671-683 |
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| 摘要 | Memory requirements (for storing intermediate signals) and critical path are the essential issues for two-dimensional (2-D) (or multi-dimensional) transforms. This work presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) Lifting-based Discrete Wavelet Transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low-transpose memory, low latency, and regular signal flow, making it suited for VLSI implementation. The transpose memory requirement of the N×N 2-D 5/3 mode LDWT and 2-D 9/7 mode LDWT are 2N and 4N, respectively. Comparison results indicate that the proposed hardware architecture has a lower lifting-based low-transpose memory size requirement than the previous architectures. As a result, it can be applied to real-time visual operations such as JPEG2000, Motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding (SVC) applications. |
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| 關鍵字 | 2-D dual-mode lifting-based discrete wavelet transform; JPEG2000; low-transpose memory |
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| 語言 | 英文 |
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| ISSN | 1051-8215 |
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| 期刊性質 | 國外 |
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| 收錄於 | SCI |
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| 產學合作 | |
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| 通訊作者 | Hsia, Chih-Hsien |
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| 審稿制度 | 是 |
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| 國別 | 美國 |
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| 公開徵稿 | |
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| 出版型式 | 紙本 |
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| 相關連結 | |
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