教師資料查詢 | 類別: 期刊論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform
學年101
學期2
出版(發表)日期2013/04/01
作品名稱Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform
作品名稱(其他語言)
著者Hsia, Chih-Hsien; Chiang, Jen-Shiun; Guo, Jing-Ming
單位淡江大學電機工程學系
出版者Piscataway:Institute of Electrical and Electronics Engineers
著錄名稱、卷期、頁數IEEE Transactions on Circuits and Systems for Video Technology 23(4), pp.671-683
摘要Memory requirements (for storing intermediate signals) and critical path are the essential issues for two-dimensional (2-D) (or multi-dimensional) transforms. This work presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) Lifting-based Discrete Wavelet Transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low-transpose memory, low latency, and regular signal flow, making it suited for VLSI implementation. The transpose memory requirement of the N×N 2-D 5/3 mode LDWT and 2-D 9/7 mode LDWT are 2N and 4N, respectively. Comparison results indicate that the proposed hardware architecture has a lower lifting-based low-transpose memory size requirement than the previous architectures. As a result, it can be applied to real-time visual operations such as JPEG2000, Motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding (SVC) applications.
關鍵字2-D dual-mode lifting-based discrete wavelet transform; JPEG2000; low-transpose memory
語言英文
ISSN1051-8215
期刊性質國外
收錄於SCI
產學合作
通訊作者Hsia, Chih-Hsien
審稿制度
國別美國
公開徵稿
出版型式紙本
相關連結
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