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標題:Ant Colony Optimization algorithm design and its FPGA implementation
學年101
學期1
發表日期2012/11/04
作品名稱Ant Colony Optimization algorithm design and its FPGA implementation
作品名稱(其他語言)
著者Li, S.A.; Yang, M.H.; Weng, C.W. ; Chen, Y.H.; Lo, C.H.; Wu, C.E.; Wong, C.C.
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on
會議地點New Taipei City, Taiwan
摘要In this paper, a Hardware/Software (HW/SW) co-design method of ant colony optimization (ACO) algorithm is proposed to implement on the FPGA chip. In this paper, the software is designed with C language and hardware is designed with Verilog hardware description language (HDL). The HW/SW co-design method is a technique based on a SOPC (System on a Programmable Chip). In this paper, the path selecting and path analysis are designed in SOPC. The path selecting belongs to the pre-processing of the ACO algorithm and it cost a longer computing processing time. Therefore, a hardware circuit is designed to speed up processing. The path analysis will be designed by the C language within the NIOS II processor. In the experimental results, the processing time can be reduced by the proposed method.
關鍵字Ant Colony Algorithm;FPGA;Hardware/Software Codesign;SOPC
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20121104~20121107
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on, pp.262-265
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