教師資料查詢 | 類別: 期刊論文 | 教師: 楊維斌 Web-bin Yang (瀏覽個人網頁)

標題:A new phase interpolator circuit for frequency multiplication design in embedded system
學年101
學期2
出版(發表)日期2013/03/01
作品名稱A new phase interpolator circuit for frequency multiplication design in embedded system
作品名稱(其他語言)
著者Yang, Wei-Bin; Wang, Chi-Hsiung; Xie, Shao-Jyun
單位淡江大學電機工程學系
出版者Japan: ICIC International
著錄名稱、卷期、頁數ICIC Express Letters 7(3A), pp.831-837
摘要The new phase interpolator circuit is proposed to double the clock frequency up to 480MHz for USB application in embedded system. The most crucial purpose is ensuring that the interpolated signal rises precisely at one-half of time interval between two complementary signals. The proposed circuit was fabricated in a 0.35μm 1P2M complementary metal-oxide-semiconductor (CMOS) process and works with a supply voltage of 3.3V. By Hspice simulation result, the measured output frequency is 480MHz with 240MHz input clock frequency. The measured jitter performance and power consumption is 10.7ps and 2.6mW, respectively. Therefore, the proposed phase interpolator circuit can be applied to 480MHz USB devices.
關鍵字
語言英文
ISSN1881-803X
期刊性質國外
收錄於EI;
產學合作
通訊作者Yang, Wei-Bin
審稿制度
國別日本
公開徵稿
出版型式,電子版
相關連結
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