教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:New memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform for JPEG2000
學年96
學期1
發表日期2008/11/19
作品名稱New memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform for JPEG2000
作品名稱(其他語言)
著者Hsia, Chih-Hsien; Chiang, Jen-Shiun
作品所屬單位淡江大學電機工程學系
出版者New York: Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference on
會議地點
摘要This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the N ?? N 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
關鍵字2-D 5/3 mode LDWT;2-D 9/7 mode LDWT;interlaced read scan algorithm (IRSA);lifting-based discrete wavelet transform (LDWT);low-transpose memory
語言英文
收錄於
會議性質
校內研討會地點
研討會時間20081119~20081121
通訊作者
國別
公開徵稿
出版型式
出處Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference on, pp.766-772
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