High-speed four-phase CMOS logic for complex high-speed VLSI
學年 80
學期 2
發表日期 1992-05-10
作品名稱 High-speed four-phase CMOS logic for complex high-speed VLSI
作品名稱（其他語言）
著者 Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 Proceedings of 1992 IEEE international symposium on circuits and systems
會議地點 San Diego, CA
摘要 A novel four-phase dynamic logic, called high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than that of the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution
關鍵字
語言 en
收錄於
會議性質 國內
校內研討會地點
研討會時間 19920510~19920513
通訊作者
國別 USA
公開徵稿 Y
出版型式 紙本
出處 Proceedings of 1992 IEEE international symposium on circuits and systems, pp.1288 - 1291
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