| Latched CMOS differential logic(LCDL)for complex high-speed VLSI | |
|---|---|
| 學年 | 78 |
| 學期 | 1 |
| 發表日期 | 1989-09-01 |
| 作品名稱 | Latched CMOS differential logic(LCDL)for complex high-speed VLSI |
| 作品名稱（其他語言） | |
| 著者 | Wu, Chung-yu; Cheng, Kuo-hsing |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | IEEE |
| 會議名稱 | Proceedings of 3rd international symposium on IC design and manufacture |
| 會議地點 | Singapore |
| 摘要 | A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | |
| 通訊作者 | |
| 國別 | SGP |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | Proceedings of 3rd international symposium on IC design and manufacture, pp.1324 - 1328 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70464 ) |
GoogleAnalytics