教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:Concurrent bit-plane coding architecture for EBCOT in JPEG2000
學年94
學期2
發表日期2006/05/21
作品名稱Concurrent bit-plane coding architecture for EBCOT in JPEG2000
作品名稱(其他語言)
著者Chiang, Jen-shiun; Hsieh, Chang-yo; Liu, Jin-chan; Chien, Cheng-chih
作品所屬單位淡江大學電機工程學系
出版者Institute of electrical and electronics engineers (IEEE)
會議名稱Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
會議地點Island of Kos, Greek
摘要This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20060521~20060524
通訊作者
國別希臘
公開徵稿Y
出版型式
出處Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp.4595-4598
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