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標題:A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
學年96
學期2
發表日期2008/04/16
作品名稱A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
作品名稱(其他語言)
著者Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱2008 The 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008)
會議地點Bratislava, Slovakia
摘要In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.
關鍵字CMOS integrated circuits;clocks;delta-sigma modulation;jitter;microwave generation;modulators
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20080416~20080418
通訊作者
國別斯洛伐克
公開徵稿Y
出版型式紙本
出處2008 The 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008),pp.1~4
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