教師資料查詢 | 類別: 會議論文 | 教師: 楊維斌 Web-bin Yang (瀏覽個人網頁)

標題:A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
學年95
學期2
發表日期2007/04/25
作品名稱A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
作品名稱(其他語言)
著者Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin
作品所屬單位淡江大學電機工程學系
出版者工業技術研究院ITRI); IEEE
會議名稱2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2007)
會議地點Hsinchu, Taiwan
摘要In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.
關鍵字
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20070425~20070427
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2007), pp.1~4
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