Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
學年 98
學期 2
發表日期 2010-05-30
作品名稱 Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
作品名稱（其他語言）
著者 饒建奇; Rau, Jiann-Chyi; Lin, Chu-Chuan; Wu, Po-Han; Chen, Gong-Han
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
會議地點 Paris, France
摘要 We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are brought by fault simulation. If still a few faults cannot be detected, the faults will be caught by directly modify the bits of ATE data. The less ATE data we use, the less cycles we need. Because the reason, we can get high speed testing. And the less data, the low-cost environment we need. The cycle we can save is up to 61.60x. And the average rate of compression can get 19.33x.
關鍵字
語言
收錄於
會議性質 國際
校內研討會地點
研討會時間 20100530~20100602
通訊作者
國別 FRA
公開徵稿 Y
出版型式
出處 Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp.437-440
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