A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
學年 95
學期 1
發表日期 2006-12-12
作品名稱 A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
作品名稱（其他語言）
著者 Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 2006 The 13th IEEE International Conference onElectronics, Circuits and Systems (ICECS '06)
會議地點 Nice, France
摘要 A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed of phase locked-loop (PLL). In this paper, a very low power-delay product divide-by 4/5 prescaler based on our DFIDFF is proposed. The prescaler implemented with 0.13 mum 1P8M N-well CMOS process with an ultra low 0.5 V power supply voltage. By HSPICE simulation results, the power-delay product (PDP) of the novel divided-by 4/5 prescaler can be reduced over 39% in comparison to conventional divided-by 4/5 prescaler. Moreover, the novel divided-by-4/5 prescaler circuit can operate at 613 MHz with the power consumption of 8.014 uW under a 0.5 V supply voltage.
關鍵字
語言 en_US
收錄於
會議性質 國際
校內研討會地點
研討會時間 20061212~20061213
通訊作者
國別 FRA
公開徵稿 Y
出版型式 紙本
出處 2006 The 13th IEEE International Conference onElectronics, Circuits and Systems (ICECS '06),pp.902 - 905
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70260 )

機構典藏連結
SDGS 優質教育,可負擔的潔淨能源,產業創新與基礎設施