教師資料查詢 | 類別: 會議論文 | 教師: 江正雄 CHIANG JEN-SHIUN (瀏覽個人網頁)

標題:High-speed EBCOT with dual context-modeling coding architecture for JPEG2000
學年92
學期2
發表日期2004/05/23
作品名稱High-speed EBCOT with dual context-modeling coding architecture for JPEG2000
作品名稱(其他語言)
著者Chiang, Jen-Shiun; Chang, Chun-Hau; Lin, Yu-Sen; Hsieh, Chang-You; Hsia ,Chih-Hsien
作品所屬單位淡江大學電機工程學系
出版者
會議名稱Circuits and Systems, 2004. ISCAS '04. the 2004 International Symposium on=2004年國際電子電機協會國際電路與系統研討會
會議地點溫哥華, 加拿大
摘要This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system, and the proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, and efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. Compared with the conventional context-modeling architecture, our parallel architecture can decrease the execution time about 25%.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20040523~20040526
通訊作者
國別加拿大
公開徵稿
出版型式
出處Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on=2004年國際電子電機協會國際電路與系統研討會論文集, v.3, pp.865-868
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