教師資料查詢 | 類別: 會議論文 | 教師: 李鴻璋 Lee Hung-chang (瀏覽個人網頁)

標題:Optimization on instruction reorganization
學年79
學期1
發表日期1990/11/27
作品名稱Optimization on instruction reorganization
作品名稱(其他語言)
著者Lai, F. ; 李鴻璋; Lee, H. C. ; Lee, C. L.
作品所屬單位淡江大學資訊管理學系
出版者IEEE
會議名稱1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23)
會議地點Orlando, Florida, USA
摘要A pipelined processor increases its performance by partitioning an instruction into several separate operation steps. Several instructions can be executed in the pipeline in different pipe stages at the same time. Because of the overlapped execution of instructions, the result of an instruction may be used before it is available. One way to solve this problem is to schedule instructions at compiler time, thus the codes generated will be free from interlocks. The scheduling algorithm presented by T. Gross (1983) and J. Hennessy and T. Gross (1983) had significantly reduced the pipeline interlocks. With some modifications to distinguish the conflict condition, the algorithm does better at the same cost.
關鍵字
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19901127~19901129
通訊作者
國別美國
公開徵稿Y
出版型式紙本
出處1990 ACM & IEEE the 23rd international symposium and workshop on Microprogramming and Microarchitecture(Micro-23), pp.143-148
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