Power-aware compression scheme for multiple scan-chain
學年 99
學期 2
出版(發表)日期 2011-06-01
作品名稱 Power-aware compression scheme for multiple scan-chain
著者 Rau, Jiann-Chyi; Wu, Po-Han
單位 淡江大學電機工程學系
出版者 Abingdon: Taylor & Francis Ltd.
著錄名稱、卷期、頁數 Journal of the Chinese Institute of Engineers 34(4), pp.515-527
摘要 As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.
關鍵字 scan based testing; low power testing; test data compression; design for testability (DfT)
語言 en
ISSN 0253-3839; 2158-7299
期刊性質 國外
收錄於 SCI
通訊作者 Rau, Jiann-Chyi
國別 GBR
出版型式 紙本 電子版

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/61044 )