教師資料查詢 | 類別: 期刊論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
學年99
學期2
出版(發表)日期2011/03/01
作品名稱An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
作品名稱(其他語言)
著者Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han
單位淡江大學電機工程學系
出版者新北市淡江大學
著錄名稱、卷期、頁數Tamkang Journal of Science and Engineering=淡江理工學刊 14(1), pp.39-48
摘要Recently, power dissipation in full-scan testing has brought a great challenge for test engineers. In addition to shift power reduction, excessive switching activity during capture operation may lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response per capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time. Experimental results for ISCAS'89 benchmark circuits show that the capture power reduction in test sequence can up to 55%.
關鍵字Clock Gating;Scan Test;Low Power Scan Test;Full-Scan Testing;Design for Testability;Yield Loss
語言英文
ISSN1560-6686
期刊性質國內
收錄於EI;
產學合作
通訊作者Rau, Jiann-Chyi
審稿制度
國別中華民國
公開徵稿
出版型式,電子版,紙本
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