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標題:High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
學年97
學期2
出版(發表)日期2009/06/01
作品名稱High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
作品名稱(其他語言)
著者Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing
單位淡江大學電機工程學系
出版者Tokyo: Denshi Jouhou Tsuushin Gakkai
著錄名稱、卷期、頁數IEICE Transactions on Electronics E92-C(6), pp.890-893
摘要A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang’s counter [1], and the E-TSPC counter [2], respectively.
關鍵字dynamic D flip-flops; counters; prescalers; ultra-low-voltage design
語言英文
ISSN0916-8524; 1745-1353
期刊性質國外
收錄於SCI;EI
產學合作
通訊作者Lo, Yu-lung
審稿制度
國別日本
公開徵稿
出版型式紙本
相關連結
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