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標題:Circuit analysis and design of low-power CMOS tapered buffer
學年91
學期2
出版(發表)日期2003/05/01
作品名稱Circuit analysis and design of low-power CMOS tapered buffer
作品名稱(其他語言)
著者Cheng, K-H; Yang, W-B
單位淡江大學電機工程學系
出版者Tokyo, Japan : Institute of Electronics, Information and Communication Engineers
著錄名稱、卷期、頁數IEICE Transactions on Electronics E86-C(5), pp.850-858
摘要Decreased power dissipation and transient voltage drops in CMOS power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits. In this paper, three CMOS buffers based on the charge-transfer, split-path and bootstrapped techniques to reduce the power dissipation and transient voltage drop in power supply are proposed. First, the inverted-delay-unit is used in the low-power inverted-delay-unit (LPID) CMOS buffer to eliminate the short-circuit current of the output stage. Second, the low-swing bootstrapped feedback-controlled split-path (LBFS) CMOS buffer is proposed to eliminate the short-circuit current of the output stage by using the feedback-controlled split-path method. The dynamic power dissipation of the LBFS CMOS buffer can be reduced by limiting the gate voltage swing of the output stage. Moreover, the propagation delay of the LBFS CMOS buffer is also reduced by non-full-swing gate voltage of the output stage. Third, the charge-recovery scheme is used in the charge-transfer feedback-controlled 4-split-path (CRFS) CMOS buffer to recovery and pull up the gate voltage of the output stage for reducing power-delay product and power line noise. Based on HSPICE simulation results, the power-delay product and the transient voltage drop in power supply of the proposed three CMOS buffers can be reduced by 20% to 40% as compared to conventional CMOS tapered buffer under various capacitive load.
關鍵字CMOS buffer; inverted-delay-unit; LPID; split-path; LBFS; low-swing bootstrapped; charge-transfer; feedback-controlled; split-path; CRFS; power-delay product
語言英文
ISSN0916-8524
期刊性質國外
收錄於SCI;EI
產學合作
通訊作者
審稿制度
國別日本
公開徵稿
出版型式紙本
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