A timing driven pseudo exhaustive testing for VLSI circuits
學年 89
學期 1
出版(發表)日期 2001-01-01
作品名稱 A timing driven pseudo exhaustive testing for VLSI circuits
著者 Chang, Shih-chieh; 饒建奇; Rau, Jiann-chyi
單位 淡江大學電機工程學系
著錄名稱、卷期、頁數 Computer-Aided design of integrated circuits and systems 20(1), pp.147-158
摘要 Because of its ability to detect all nonredundant combinational faults, exhaustive testing, which applies all possible input combinations to a circuit, is an attractive test method. However, the test application time for exhaustive testing can be very large. To reduce the test time, pseudoexhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each node is within some predetermined value. Though bsc insertion can reduce the test time, it may increase circuit delay, In this paper, our objective is to reduce the delay penalty of bsc insertion for pseudoexhaustive testing. We first propose a tight delay lower bound algorithm, which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, ne can propose a bsc insertion heuristic that tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.
語言 en
期刊性質 國內
國別 TWN
出版型式 ,電子版

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60771 )