教師資料查詢 | 類別: 期刊論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
學年89
學期1
出版(發表)日期2000/10/01
作品名稱Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
作品名稱(其他語言)
著者Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L.
單位淡江大學電機工程學系
出版者The Institution of Engineering and Technology(IET)
著錄名稱、卷期、頁數IEE Proceedings - Computers and Digital Techniques 147(5), pp.343-348
摘要A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging
關鍵字
語言英文
ISSN1350-2387;1359-7027
期刊性質國外
收錄於SCI;EI
產學合作
通訊作者
審稿制度
國別英國
公開徵稿
出版型式紙本;電子版
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