| Latched CMOS differential logic(LCDL)for complex high-speed VLSI | |
|---|---|
| 學年 | 80 |
| 學期 | 1 |
| 出版（發表）日期 | 1991-09-01 |
| 作品名稱 | Latched CMOS differential logic(LCDL)for complex high-speed VLSI |
| 作品名稱（其他語言） | |
| 著者 | Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 著錄名稱、卷期、頁數 | IEEE Journal of Solid-State Circuits 26(9), p.1324-1328 |
| 摘要 | A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL. |
| 關鍵字 | CMOS logic circuits;Very large scale integration;Clocks;Logic functions;Logic circuits;Switches;Pipelines;Voltage;MOS devices;Power dissipation |
| 語言 | en_US |
| ISSN | 1558-173X;0018-9200 |
| 期刊性質 | 國外 |
| 收錄於 | |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | USA |
| 公開徵稿 | |
| 出版型式 | ,電子版,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60698 ) |
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