A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching | |
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學年 | 93 |
學期 | 2 |
發表日期 | 2005-06-14 |
作品名稱 | A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching |
作品名稱(其他語言) | |
著者 | 郭建宏; Kuo, Chien-hung; Tsai, Jen-chieh |
作品所屬單位 | 淡江大學電機工程學系 |
出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
會議名稱 | Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on |
會議地點 | Macau, China |
摘要 | A low-power digital-to-analog converter for portable electronics is introduced A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18 μm 1P6M CMOS standard technology, and its core area is 0.27 mm2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10 MHz, and consume 2.5 mW of power from a 1.8 V supply voltage. |
關鍵字 | |
語言 | en |
收錄於 | |
會議性質 | 國際 |
校內研討會地點 | |
研討會時間 | 20050614~20050616 |
通訊作者 | |
國別 | MAC |
公開徵稿 | |
出版型式 | 紙本 |
出處 | Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on, pp.473-477 |
相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38797 ) |