A difference detector PFD for low jitter PLL
學年 90
學期 1
發表日期 2001-09-02
作品名稱 A difference detector PFD for low jitter PLL
作品名稱（其他語言）
著者 鄭國興; Cheng, Kuo-hsing; Yao, Tse-hua; Jiang, Shu-yu; Yang, Wei-bin
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
會議地點 Malta
摘要 For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6 GHz. Furthermore, with difference detector, the dd-PFD has three states, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16 ps. The proposed PFD is designed using 0.35 μm CMOS technology at 3.3 V power supply.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20010902~20010905
通訊作者
國別 MLT
公開徵稿
出版型式 紙本
出處 Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on (Volume:1 ), pp.43-46
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