| Programmable fractional-N clock generators | |
|---|---|
| 學年 | 94 |
| 學期 | 1 |
| 專利開始日期 | 2005-09-23 |
| 專利結束日期 | 2005-09-23 |
| 作品名稱 | Programmable fractional-N clock generators |
| 作品名稱（其他語言） | |
| 著者 | 郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
| 單位 | 淡江大學電機工程學系 |
| 著錄名稱、卷期、頁數 | |
| 描述 | 專利國別：美國 United States Patent: 7,242,231 Application number: 11/232,949 國際分類號：H03L 7/06 |
| 摘要 | Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D.sub.0.about.D.sub.m) with a first frequency (f0), in which the first clocks D.sub.i and D.sub.i-1 have a fixed phase difference and 1<i<m. A logic control circuit outputs a set of corresponding clocks arranged in a corresponding sequence according to the first clocks and a binary code. A clock synthesizer generates a second clock with a second frequency (f1) according to the set of corresponding clocks, in which f1=A/B f0, A<B and A and B are positive integers. |
| 關鍵字 | |
| 語言 | en |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/53896 ) |
| SDGS | 消除貧窮,產業創新與基礎設施 |
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