關鍵字查詢 | 類別:會議論文 | | 關鍵字:Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture

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序號 學年期 教師動態
1 94/1 電機系 江正雄 教授 會議論文 發佈 Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture , [94-1] :Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture會議論文Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI ArchitectureHsia, Chih-Hsien; Chiang, Jen-Shiun; Huang, Ting-Wei淡江大學電機工程學系Discrete wavelet transform (DWT);Interlaced read scan algorithm(IRSA);Lifting-based DWT;Multiresolution;On-chip memory;Real-time2005民生電子暨信號處理研討會論文集=Proceedings of Workshop on Consumer Electronics and Signal Processing,6頁雲林科技大學工程學院電機工程系;影音壓縮推動聯盟;工研院光電所; 雲林科技大學資訊工程所;工研院電通所;中華電信研究所; 行政院國家科學委員會工程科技推展中心;工研院電子所;資訊工業策進會This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architecture has the advantages of lower com
2 94/1 電機系 夏至賢 助理教授 會議論文 發佈 Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture , [94-1] :Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture會議論文Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI ArchitectureHsia, Chih-Hsien; Chiang, Jen-Shiun; Huang, Ting-Wei淡江大學電機工程學系Discrete wavelet transform (DWT);Interlaced read scan algorithm(IRSA);Lifting-based DWT;Multiresolution;On-chip memory;Real-time2005民生電子暨信號處理研討會論文集=Proceedings of Workshop on Consumer Electronics and Signal Processing,6頁雲林科技大學工程學院電機工程系;影音壓縮推動聯盟;工研院光電所; 雲林科技大學資訊工程所;工研院電通所;中華電信研究所; 行政院國家科學委員會工程科技推展中心;工研院電子所;資訊工業策進會This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architecture has the advantages of lower com
3 94/1 電機系 江正雄 教授 會議論文 發佈 Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture , [94-1] :Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture會議論文Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI ArchitectureHsia, Chih-Hsien; Chiang, Jen-Shiun; Huang, Ting-Wei淡江大學電機工程學系Discrete wavelet transform (DWT); Interlaced read scan algorithm(IRSA); Lifting-based DWT; Multiresolution; On-chip memory; Real-time雲林縣:雲林科技大學2005民生電子暨信號處理研討會論文集;Proceedings of Workshop on Consumer Electronics and Signal Processing, 6p.雲林科技大學工程學院電機工程系; 影音壓縮推動聯盟; 工業技術研究院電子與光電研究所; 雲林科技大學資訊工程所; 工業技術研究院電腦與通訊研究所; 中華電信研究所; 行政院國家科學委員會工程科技推展中心; 資訊工業策進會This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architectur
4 94/1 電機系 夏至賢 助理教授 會議論文 發佈 Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture , [94-1] :Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI Architecture會議論文Design of High-Efficiency Multimedia Signal Processing IP for 2-D DWT VLSI ArchitectureHsia, Chih-Hsien; Chiang, Jen-Shiun; Huang, Ting-Wei淡江大學電機工程學系Discrete wavelet transform (DWT); Interlaced read scan algorithm(IRSA); Lifting-based DWT; Multiresolution; On-chip memory; Real-time雲林縣:雲林科技大學2005民生電子暨信號處理研討會論文集;Proceedings of Workshop on Consumer Electronics and Signal Processing, 6p.雲林科技大學工程學院電機工程系; 影音壓縮推動聯盟; 工業技術研究院電子與光電研究所; 雲林科技大學資訊工程所; 工業技術研究院電腦與通訊研究所; 中華電信研究所; 行政院國家科學委員會工程科技推展中心; 資訊工業策進會This work presents novel algorithms and hardware architectures to improve the critical issue of 2-D discrete wavelet transform (DWT). On-chip memory cost is a very important problem in multimedia IC design. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and pipeling scheme processing to achieve low-memory size and high-speed operation. The proposed lifting-based DWT architectur
[第一頁][上頁]1[次頁][最末頁]目前在第 1 頁 / 共有 04 筆查詢結果