關鍵字查詢 | 類別:會議論文 | | 關鍵字:Ant Colony Optimization algorithm design and its FPGA implementation

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序號 學年期 教師動態
1 101/1 電機系 李世安 副教授 會議論文 發佈 Ant Colony Optimization algorithm design and its FPGA implementation , [101-1] :Ant Colony Optimization algorithm design and its FPGA implementation會議論文Ant Colony Optimization algorithm design and its FPGA implementationLi, S.A.; Yang, M.H.; Weng, C.W. ; Chen, Y.H.; Lo, C.H.; Wu, C.E.; Wong, C.C.淡江大學電機工程學系Ant Colony Algorithm;FPGA;Hardware/Software Codesign;SOPCInstitute of Electrical and Electronics Engineers (IEEE)Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on, pp.262-265In this paper, a Hardware/Software (HW/SW) co-design method of ant colony optimization (ACO) algorithm is proposed to implement on the FPGA chip. In this paper, the software is designed with C language and hardware is designed with Verilog hardware description language (HDL). The HW/SW co-design method is a technique based on a SOPC (System on a Programmable Chip). In this paper, the path selecting and path analysis are designed in SOPC. The path selecting belongs to the pre-processing of the ACO algorithm and it cost a longer computing process
2 101/1 電機系 翁慶昌 教授 會議論文 發佈 Ant colony optimization algorithm design and its FPGA implementation , [101-1] :Ant colony optimization algorithm design and its FPGA implementation會議論文Ant colony optimization algorithm design and its FPGA implementationS.A. Li, M.H. Yang, C.W. Weng, Y.H. Chen, C.H. Lo, C.E. Wu, and C.C. Wong電機工程學系暨研究所tku_id: 000078414;Submitted by 慶昌 翁 (078414@mail.tku.edu.tw) on 2013-02-18T06:43:51Z No. of bitstreams: 0;Made available in DSpace on 2013-02-18T06:43:52Z (GMT). No. of bitstreams: 0zh_TW國際20121105~201211072012 IEEE International Symposium on Intelligent Signal Processing and Communication SystemsTamsui, Taiwan<links><record><name>機構典藏連結</name><url>http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/80574</url></record></links>
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