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序號 學年期 教師動態
1 89/2 電機系 鄭國興 副教授 會議論文 發佈 A new logic synthesis and optimization procedure , [89-2] :A new logic synthesis and optimization procedure會議論文A new logic synthesis and optimization procedure鄭國興; Cheng, Kuo-hsing; Hsieh, Ven-chieh淡江大學電機工程學系Institute of Electrical and Electronics Engineers (IEEE)Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.tku_id:000094759;Made available in DSpace on 2010-04-15T03:38:53Z (GMT). No. of bitstreams: 1
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