關鍵字查詢 | 類別:會議論文 | | 關鍵字:A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic

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1 86/1 電機系 鄭國興 副教授 會議論文 發佈 A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic , [86-1] :A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic會議論文A 1.2V Low-Power TSPC Complementary Pass-Transistor LogicCheng, Kuo-Hsing; Chen, Jian-Hung淡江大學電機工程學系互補式被動電晶體邏輯;真實單相時序;低功率;緩衝器;電路模擬;Complementary Pass-Transistor Logic;True-Single-Phase Clock;Low Power;Buffer;Circuit Simulation第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium,頁357-360中央研究院; 台灣大學電機工程系; 教育部This paper describes a new low-voltage low-power TSPC complementary pass-transistor logic circuit for 1.2V applications. The proposed logic circuits are implemented with only NMOS differential pass- transistor logic network and controlled by true-single-phase clock signal to form the pipelined structures. Due to the limited voltage swing and current-sensing scheme, the proposed TSPC logic circuits have certain advantages in both operation speed and power dissipation. Moreover, it can be designed and fabricated without changing the conventional 5V, 0.6μm CMOS process. Based upon the HSPICE s
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