關鍵字查詢 | 類別:會議論文 | | 關鍵字:A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process

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1 86/1 電機系 鄭國興 教授 會議論文 發佈 A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process , [86-1] :A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process會議論文A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS ProcessCheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin淡江大學電機工程學系加法器;互補式金氧半導體;架構;效能比較;方塊圖;Adder;Cmos;Architecture;Performance Comparison;Block Diagram第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium,頁349-352中央研究院; 台灣大學電機工程系; 教育部This paper describes circuit techniques for fabricating a 1.2V high-speed 32-bit adder using pass-transistor logic and without changing conventional 5V CMOS process. The low- power current-sensing complementary pass-transistor logic(LCSCPTL) is used in this design for its high operating speed and low power dissipation. A carry propagation circuit technique called conditional carry selection ( CCS) is used to resolve the problem of series-connected pass transistors in the carry propagation path. Based upon the HSPICE simulation, the operation speed of the LCSCPTL is about 2.2 times highe
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